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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__hdmitx_8h.html" title="This is the main header file for Xilinx HDMI TX core. ">xv_hdmitx.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
----- ------ -------- --------------------------------------------------
1.00         10/07/15 Initial release.</pre><pre></pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a3eafe27fd10317ecb42fe689ca593212"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>&#160;&#160;&#160;(0*64)</td></tr>
<tr class="separator:a3eafe27fd10317ecb42fe689ca593212"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec908667ddf1597c82b2d5c16c21ca87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aec908667ddf1597c82b2d5c16c21ca87">XV_HDMITX_VER_VERSION_OFFSET</a>&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(1*4))</td></tr>
<tr class="separator:aec908667ddf1597c82b2d5c16c21ca87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53a26ad8c741bb6defdabaf539c15f76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a53a26ad8c741bb6defdabaf539c15f76">XV_HDMITX_PIO_IN_PPP_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="separator:a53a26ad8c741bb6defdabaf539c15f76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41b837de9bdbba60a15baa46362dd851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a41b837de9bdbba60a15baa46362dd851">XV_HdmiTx_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a90f7af607960cdf44deb2b43aab27254">XV_HdmiTx_In32</a>((BaseAddress) + ((u32)RegOffset))</td></tr>
<tr class="separator:a41b837de9bdbba60a15baa46362dd851"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b74e3c052543284012c23ec717af9d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3b74e3c052543284012c23ec717af9d1">XV_HdmiTx_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a6038ccff274de8b99efc34332d0c41d9">XV_HdmiTx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td></tr>
<tr class="separator:a3b74e3c052543284012c23ec717af9d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a30dbe14665ee4c6b2ef5188837430071"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_ACR_CTS_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Clock Regeneration CTS * Register offset. </p>

</div>
</div>
<a class="anchor" id="a702529bf17d853efb695aef1898fba3b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_ACR_N_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Clock Regeneration N * Register offset. </p>

</div>
</div>
<a class="anchor" id="a28f589dcdb02f0836911bc48271fca9b"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_CH_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control channels mask. </p>

</div>
</div>
<a class="anchor" id="a224d3ce0b2fa5396ac35464ab51e18c0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_CH_SHIFT&#160;&#160;&#160;2</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control channels mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="a487977b6c692a3cabd9708d199cc6fde"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Clear * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="ab6d28afc44db8a26bcd45f828afc5d01"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1f37ae939243ded094b88763c8fbcc76"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="a72bdef52359446483eab0a4b6886ba34"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Run mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="a0657ebf695c90d411c0ecd63aed71d96"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Set * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

</div>
</div>
<a class="anchor" id="aa3e1bf1acca1da7e3668b1664ee82fd3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a26011fe634f2296a975829bae26517fe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Interrupt mask. </p>

</div>
</div>
<a class="anchor" id="a7caf30398bed7b2964861a29271c0bd6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Register * offset. </p>

</div>
</div>
<a class="anchor" id="a2f87dd0bb31f82655eabba7db6189540"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a060b91563a63af214d8ca983278d38eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a650c485d8b048a53058d7a55953db647"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="a586d49d608b7effcbd9176c782ca59da"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Run mask. </p>

</div>
</div>
<a class="anchor" id="aa9117e3cd8d01675a6a9db523a49807e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="ab4ffb246932642063518c85c719350a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_DAT_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Data Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a06fa3ff9976df2241535d4538a8e4f69">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="a5b8e97815f844573c8549f0b9f8c805c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a4ba5033c98cfedf815f51ea6c76cb0ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FIFO_EMT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Empty mask. </p>

</div>
</div>
<a class="anchor" id="a471c6374f04e71189d48849b294155de"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FIFO_FUL_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Full mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a06fa3ff9976df2241535d4538a8e4f69">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="a92d6d522c60806a380ed5a6aee2c620c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FREE_PKTS_MASK&#160;&#160;&#160;0x0F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Free Packets mask. </p>

</div>
</div>
<a class="anchor" id="adc1a9c1d2d63c4849f8fc776838f01cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Free Packets shift. </p>

</div>
</div>
<a class="anchor" id="a5664a354bf22aa9e19d950a18c9598f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Interrupt mask. </p>

</div>
</div>
<a class="anchor" id="aadeed071f9ae80ff300b531ea298f42a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a06fa3ff9976df2241535d4538a8e4f69">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="a7356d56189f12a10c6f79a97012e3882"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Command Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="a77fe4475732ac1844f33515e64590bd0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_RD_TOKEN&#160;&#160;&#160;(0x102)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>.</p>

</div>
</div>
<a class="anchor" id="a17aefbf8e9a56021a1fa7321fca45995"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_STP_TOKEN&#160;&#160;&#160;(0x101)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stop token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>, and <a class="el" href="xv__hdmitx_8h.html#a852ea29dc77f7bff5509cbf7fe935ede">XV_HdmiTx_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="ab6901facaddc25fe1f07d0eee6e65908"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_STR_TOKEN&#160;&#160;&#160;(0x100)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Start token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>, and <a class="el" href="xv__hdmitx_8h.html#a852ea29dc77f7bff5509cbf7fe935ede">XV_HdmiTx_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="a0a3e0ff5b586f637f7ce58e37e76a0d4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_WR_TOKEN&#160;&#160;&#160;(0x103)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Write token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>, and <a class="el" href="xv__hdmitx_8h.html#a852ea29dc77f7bff5509cbf7fe935ede">XV_HdmiTx_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="a1e7d988ba6707bb1cd58fa9af9db6ae0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_CLK_DIV_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Clock Divider mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a3fe50d870f063d85a274d2cbe9dee549">XV_HdmiTx_DdcInit()</a>.</p>

</div>
</div>
<a class="anchor" id="a0183fc18bbe56540d95fc291e3060c38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a0b2d0351f601ac8afdc99e651a916111"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="afaed19df9105685cea7b51363e5aab38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a3fe50d870f063d85a274d2cbe9dee549">XV_HdmiTx_DdcInit()</a>.</p>

</div>
</div>
<a class="anchor" id="a25f1a215971c5370677b19e3b9f16bf2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Run mask. </p>

</div>
</div>
<a class="anchor" id="aab4ea6581cb2fd09a5aabd906da25b17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="aafc52187f15507e2b6b6f7438ddb3c8c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_DAT_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Data Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>.</p>

</div>
</div>
<a class="anchor" id="a4af3a11ac2e2a2190f6e8c39111199d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="af77c4ab50461a2356e62aaa8fa279bab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_ACK_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status ACK mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#abdb511167dc499eacf28789225e83a24">XV_HdmiTx_DdcGetAck()</a>.</p>

</div>
</div>
<a class="anchor" id="ad2f3f71a213bc05457101200b03d2ebe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_BUSY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

</div>
</div>
<a class="anchor" id="a108fb0a980dd01604d286d675f001a21"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_CMD_FULL&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo full. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="ab64afd200f27ec3c82835a75eca6f61c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_CMD_WRDS_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo words mask. </p>

</div>
</div>
<a class="anchor" id="a14e07ba89f7f88769f399f1e7fa640dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo words shift. </p>

</div>
</div>
<a class="anchor" id="ab39f53e62517e7756ccaae1972635e71"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DAT_EMPTY&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo empty. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>.</p>

</div>
</div>
<a class="anchor" id="a453c5f4507cb2b4d399eb0f778ccf934"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DAT_WRDS_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo words mask. </p>

</div>
</div>
<a class="anchor" id="a59938ef823d937157bdbe0ffd06ed0d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo words shift. </p>

</div>
</div>
<a class="anchor" id="a5c2fcc8362b12929e9069f044c452bd7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DONE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>.</p>

</div>
</div>
<a class="anchor" id="ad944d773e9619b1d2076aa5bc0d9f4e2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Event mask. </p>

</div>
</div>
<a class="anchor" id="aed853aca89756ea743e083e7573d1617"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status IRQ mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="add689faff8e7c346c9d8202355678a22"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#abdb511167dc499eacf28789225e83a24">XV_HdmiTx_DdcGetAck()</a>, <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>, and <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ab98e29e866183af70534dbf21deb4963"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_SCL_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC State of SCL Input mask. </p>

</div>
</div>
<a class="anchor" id="ae486edb257d9135145951631a6b4b110"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_SDA_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC State of SDA Input mask. </p>

</div>
</div>
<a class="anchor" id="ab4cc4517f9d2cdacd81718603c6a2308"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_TIMEOUT_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Timeout mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>.</p>

</div>
</div>
<a class="anchor" id="a0711485d228f909cc65b275f866e526c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="a90f7af607960cdf44deb2b43aab27254"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="a74530507b4700c300feb4eceed05668f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_16&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a6038ccff274de8b99efc34332d0c41d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="ad1d5bdab7fa4daf868d93d2edd96f566"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a912027acfdcf62f09ebcb9c4eafb1a74"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a09b04c19ceb81d2b9e5064d53e232e17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="a40a412194d70fcbb53cef17eea048fa3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a8e98120a6a24452d2865d24f740129b1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="a5131cd2488ca4a797d71849293cc1109"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_ID&#160;&#160;&#160;0x2200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TX's PIO ID. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a0f3575afd1ca4f63ffa6c725ff78ee7d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Identification * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="ab26c31b92aedb7564284403ca2db65f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_EVT_FE_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Falling Edge * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a5393d399e287df6c50b6c32b90b1cf93"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_EVT_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Register * offset. </p>

</div>
</div>
<a class="anchor" id="a50a497ec4e91768009efd7752e7ed9f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_EVT_RE_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Rising Edge * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a38b7234925ae25a8a5104c446e2b0c50"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_HPD_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In HPD mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="af84ed4e0a3e63ee5b5eeb18b5f9172f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_LNK_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In link ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ae1aa781005ce21dab9e7af6e4c091d0e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Register offset. </p>

</div>
</div>
<a class="anchor" id="afe3ba46026108ca4004a2c1f4e175cda"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_PPP_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Pixel packing phase mask. </p>

</div>
</div>
<a class="anchor" id="a53a26ad8c741bb6defdabaf539c15f76"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_PPP_SHIFT&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Pixel packing phase shift. </p>
<p>DDC (Display Data Channel) peripheral register offsets The DDC is the second peripheral on the local bus </p>

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<a class="anchor" id="a8eae374abecb5156f5827c2543467866"></a>
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          <td class="memname">#define XV_HDMITX_PIO_IN_VID_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In video ready mask. </p>

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<a class="anchor" id="a5e6881f3d1d651347a8e507c6d708aa6"></a>
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          <td class="memname">#define XV_HDMITX_PIO_IN_VS_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Vsync mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>.</p>

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<a class="anchor" id="a57cd09ceda16cfc89ad51ab5fd16c625"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_OUT_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Clear * offset. </p>

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<a class="anchor" id="a564d1abff6cb04057811a461cfbcb692"></a>
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          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Depth mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>.</p>

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<a class="anchor" id="aa3936d875363ae229e89ab0d93005173"></a>
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          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Depth shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>.</p>

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<a class="anchor" id="a461cc5f1205b18c92863bbd3042540b7"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK&#160;&#160;&#160;0xC00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>.</p>

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<a class="anchor" id="ac01a89ba24d5a2044caa1377a5aea7aa"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>.</p>

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<a class="anchor" id="a8b22105cf60c90514691a778c3652769"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_OUT_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mode mask. </p>

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<a class="anchor" id="a3aec0a8a571c50309c582ac0a3a66cda"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_OUT_MSK_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mask Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>, <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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</div>
<a class="anchor" id="a73655a77916a05b7d8f82a921f15f7be"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>, <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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</div>
<a class="anchor" id="a92829fb1e590c09d7cb030093ed38ba3"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK&#160;&#160;&#160;0xC0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>.</p>

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</div>
<a class="anchor" id="ad507e1024a352cdf174c99ade627b5fb"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>.</p>

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</div>
<a class="anchor" id="a3492813bb70421de0a228014bf8d949b"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_RST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Reset mask. </p>

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<a class="anchor" id="ad69a761dfc73ee26434f08f27c83dcdf"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK&#160;&#160;&#160;0x300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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</div>
<a class="anchor" id="ae81b504f82f4bb53a7f6340c91b722f5"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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</div>
<a class="anchor" id="aec658e14a00798e20cec912c330c4d0d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SCRM_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Scrambler mask. </p>

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<a class="anchor" id="afb3e424d18e1c4b146232b67699824eb"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Set * offset. </p>

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<a class="anchor" id="aca60ad2b7145ae20f665c42136e63bb7"></a>
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<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Event mask. </p>

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<a class="anchor" id="aa8c178b5851211ca5b20faee275a73f8"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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      </table>
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<p>PIO Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="a9374a3f25d4d9c91c02d383d66443b4b"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(4*4))</td>
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      </table>
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<p>PIO Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

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<a class="anchor" id="a41b837de9bdbba60a15baa46362dd851"></a>
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          <td class="memname">#define XV_HdmiTx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a90f7af607960cdf44deb2b43aab27254">XV_HdmiTx_In32</a>((BaseAddress) + ((u32)RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a HDMI TX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmitx__hw_8h.html#a41b837de9bdbba60a15baa46362dd851" title="This macro reads a value from a HDMI TX register. ">XV_HdmiTx_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a06fa3ff9976df2241535d4538a8e4f69">XV_HdmiTx_AuxSend()</a>, <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>, <a class="el" href="xv__hdmitx_8c.html#abdb511167dc499eacf28789225e83a24">XV_HdmiTx_DdcGetAck()</a>, <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

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<a class="anchor" id="ab077de545e32c541e6e01a9d78fdade2"></a>
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<div class="memproto">
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          <td class="memname">#define XV_HDMITX_SHIFT_16&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 shift value </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

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</div>
<a class="anchor" id="a3eafe27fd10317ecb42fe689ca593212"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_VER_BASE&#160;&#160;&#160;(0*64)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; VER (Version Interface) peripheral register offsets </p>
<p>&lt; The VER is the first peripheral on the local bus </p>

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</div>
<a class="anchor" id="a7f0f14a5d0d925bbff6d86e79678300a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_VER_ID_OFFSET&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Identification * Register offset. </p>

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</div>
<a class="anchor" id="aec908667ddf1597c82b2d5c16c21ca87"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_VER_VERSION_OFFSET&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Version Register * offset. </p>
<p>PIO (Parallel Interface) peripheral register offsets The PIO is the first peripheral on the local bus </p>

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<a class="anchor" id="a3b74e3c052543284012c23ec717af9d1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a6038ccff274de8b99efc34332d0c41d9">XV_HdmiTx_Out32</a>((BaseAddress) + ((u32)RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes a value to a HDMI TX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx__hw_8h.html#a3b74e3c052543284012c23ec717af9d1" title="This macro writes a value to a HDMI TX register. ">XV_HdmiTx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a06fa3ff9976df2241535d4538a8e4f69">XV_HdmiTx_AuxSend()</a>, <a class="el" href="xv__hdmitx_8h.html#a9ceb7647f6286ebc4b5b89825884d7f5">XV_HdmiTx_CfgInitialize()</a>, <a class="el" href="xv__hdmitx_8h.html#a3fe50d870f063d85a274d2cbe9dee549">XV_HdmiTx_DdcInit()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>, <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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